[R-390] Best approach for SSB mod on R-390A

[2002tii]

Steve wrote:

>If you were designing a PLL synchronous detector that attempted to 
>maintain phase coherence during a selective fade lasting several 
>seconds, what loop bandwidth would you choose?  Given such a loop 
>bandwidth, how would you arrange to achieve lock after tuning the 
>receiver without waiting an inordinate period of time?

Those are the right questions to start with.  The first thing one has 
to do is hard limit the signal to make sure one has evey scrap of 
carrier available.  Then, one needs to use a number of techniques to 
ameliorate the various kinds of disturbances encountered in radio reception.

As you recognize, the primary loop time constant should be large to 
handle slow fades, but this limits the speed and can limit the range 
of acquisition when the loop is unlocked.  Using higher-order loop 
filters can help to reconcile these divergent requirements, and a 
reasonable synchronous detector can be made this way if one is very 
careful with the loop design.  But IMO, a good synch detector for a 
communications radio requires a loop envelope larger than what can be 
achieved by this means alone.  I have used three additional 
techniques to make detectors that have good acquisition range (+/- 1 
kHz is about right, IME), reach lock quickly, and hold lock during 
long fades: dynamically variable loop gain; dynamically variable loop 
bandwidth and order; and oscillator clamping.  How one deploys these 
techniques depends on the ergonomics one wants to achieve.

One ergonomic approach is to design a slow, first-order loop with a 
limited capture range.  If not well designed, such a system may 
require manual guidance to achieve lock.  In any case, such systems 
are difficult to tune accurately.  As I have said before, I believe 
each of these characteristics is intolerable in a synchronous 
detector.  Another ergonomic approach, exemplified by the Drake R8B, 
is to disable the synchronous detector and speed up the PLL loop 
filter during tuning -- this avoids hearing carrier heterodynes while 
tuning, and allows a larger capture range and faster acquisition 
while not sacrificing tenacity of lock.  Personally, I prefer hearing 
carrier heterodynes while tuning -- thus, for my own use, I prefer to 
clamp the BFO to its nominal (center) frequency during tuning, and 
leave the product detector operating.  When tuning stops and the 
clamp is released, the fastest loop parameters are engaged.  As lock 
is approached, slower loop coefficients are selected.  As with the 
R8B scheme, this is easier if the detector is in the same box with 
the main VFO and a "tuning in progress" flag is available, but there 
are any number of parameters one can detect and use to manage the 
switching of loop bandwidth/order, gain, and clamping without having 
such a signal.  Clamping (not to center, but to the last locked 
frequency) is also very helpful in dealing with long fades when the 
carrier goes to zero and stays there.

Here is a pretty decent introduction to PLL design (best free 
tutorial I know of), which discusses some of these techniques:

http://www.national.com/appinfo/wireless/files/deansbook4.pdf

Best regards,

Don