[GPS_Standard] Interesting paper

[Bob Stewart]

Hi Glenn,

Let me preface this firmly with the statement that I am not a control systems expert.  So, with that proviso:

We have several problems to deal with.  First and foremost in my mind has been the Oncore GPS receiver.  It's a nice receiver, but Bert's board has no way of dealing with a PPS signal that can vary as much as 374 degrees between two pulses.  Those don't happen often, no, but the output tends to a few types of patterns.  One is the rare 374 degree excursion.  Another is excursions that are over 360 degrees, but not 374.  Another is those that are over 180 degrees but less than 360.  And of course, the matching less than 180 degrees.  Sounds good, if it was clean, but it's not.  It suffers from many periods of phase error bias.  IOW, it may stay in a positive phase error for a long period of time.  This may or may not be followed by a long period in a negative phase error.  But, in a nutshell, we cannot know the condition of the phase of the 1PPS signal output from the Oncore - as it relates to the phase error we detect - so it's an unsuitable
 receiver for anything other than long term frequency averaging.  Of course, it's possible that someone brighter than me could come up with a solution I failed to see using the Sawtooth and One Sigma Error outputs of the Oncore.  But, then you'd either have to run correction software on the PC, or complicate the comms interface to the PIC chip by sharing TX and RX pins somehow between the PC and the Oncore from Bert's board.

Another problem is the 10-bit DAC.  Bert did a nice job of using dithering to increase it to 14 bits, but it's still of marginal size for our needs, and the dithering poses a phase problem when we need to change one of the least significant bits.  Bert got around that by just letting it settle out for awhile before beginning a sample pass.  It's not quite as easy when you need to use a signal that is noisy in phase to tightly control the phase of another signal.

Now, on closer in is the difference between frequency and phase.  Bert's simple test for the count of cycles between 1PPS pulses serves pretty well.  For large differences, we know we have a frequency error.  For small differences a phase error. But, frequency errors can be considered as phase errors, and so it works as a phase detector, but at a cost.  There is a large dead zone that is immediately apparent when you look at the phase charts I've been posting.

And, on to the detection and correction of a phase error.  In the case where the slope of the phase error is large, things work out pretty well, as it is more nearly a frequency error, even at very small errors.  When the slope gets small enough though, we have the problem of "where is the DAC voltage in relation to the phase error?"  If the control voltage needed for zero phase error lies exactly between two values of the DAC, it is pretty easy to tick-tock back and forth to keep it there - barring drift.  Once the oscillator drifts a bit, it becomes harder to manage.  

Now, imagine using two DAC values as a PWM.  With our imaginary PWM, as zero phase drifts toward one side, we can change the duty cycle to correct for it until we can't.  Once the drift pushes it past our PWM's capture zone, we have one of two choices:  1) Wait many minutes for the phase point to come back into capture range, or 2) issue an update to the DAC that will hopefully move our imaginary PWM enough to recapture the phase point without putting so much velocity into the oscillator delta that we fly through the zero phase point and have to correct, still again.


Again, I am not a control systems professional.  I apologize for errors in terminology in the above.  Hopefully at least my thought processes are correct and understandable.


Bob




>________________________________
> From: Glenn Elmore <n6gn at sonic.net>
>To: gps_standard at mailman.qth.net 
>Sent: Monday, November 18, 2013 3:08 PM
>Subject: Re: [GPS_Standard] Interesting paper
> 
>
>Is this problem not similar to the reason for using a phase/frequency comparator from traditional PLL design?  With that, the error smoothly measure 4pi radians of error between two rails providing phase detection. In conditions where the reference and VCO are more than one reference cycle apart, there is cycle slip, the error rails in the direction of the frequency error and the part provides frequency detection.  Having this dual mode allows a lock range that is greater than the loop bandwidth.
>
>Perhaps a digital simulation of this (analog) functionality has some merit. Or perhaps I'm just missing the boat :-)
>
>Glenn n6gn
>
>