[GPS_Standard] Interesting paper

[Glenn Elmore]

Is this problem not similar to the reason for using a phase/frequency 
comparator from traditional PLL design?  With that, the error smoothly 
measure 4pi radians of error between two rails providing phase 
detection. In conditions where the reference and VCO are more than one 
reference cycle apart, there is cycle slip, the error rails in the 
direction of the frequency error and the part provides frequency 
detection.  Having this dual mode allows a lock range that is greater 
than the loop bandwidth.

Perhaps a digital simulation of this (analog) functionality has some 
merit. Or perhaps I'm just missing the boat :-)

Glenn n6gn


On 11/18/2013 01:01 PM, Bob Stewart wrote:
> Dave says:
> "As I understand it (from the technology and from reading Shera's original QST article) the PLL approach comes along with one fairly stern requirement:  you have to manually tune the oscillator to within a gnat's whisker before it can phase-lock.  It has a narrow capture range.  My guess is that if you haven't already tuned the oscillator to within a fraction of one cycle per sample-averaging period, it won't lock"
>
> Dave, I have experienced this myself in code that I haven't released, but hope to, in time.  This is the one we discussed, where I had a pretty tight lock, and when it fell out of the capture zone I issued another DAC update to attempt to push it back in.  However, with my version, it's not necessary to manually set things up.  It reaches the "zone" pretty quickly.  The problem is keeping it there.
>
> Bob
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