[GPS_Standard] Fw: GPSstd_PLL testing: V0.13 with an improved State Machine 2

[Bob Stewart]

Hi Michal,

Regarding the result of the PN2222A inversion, 
wouldn't it be enough just to change the code to monitor the falling 
edge instead of the rising edge?  I haven't done that yet.  I think on 
my next compile I'll give it a shot.

Bob




________________________________
 From: SP2IQW <michal at e2000.gdynia.pl>
To: gps_standard at mailman.qth.net 
Cc: Bob Stewart <bob at evoria.net> 
Sent: Thursday, November 14, 2013 5:44 PM
Subject: Re: [GPS_Standard] GPSstd_PLL testing: V0.13 with an improved State Machine 2
 
Hi Bob and All,

I'm carefully observing your software work on improving Berts's GPSDO.
Few
 years ago I have build VE2ZAZ GPSDO with some hardware rework. To 
eliminate jitter caused by noisy and not so stable 5V PS line I have 
added uA723 based 5V voltage regulator supplying only CMOS buffer 
(non-inverting) on the PWM output.

As per GPS, your choice to use
 MTK-chipset means current "state of art" within simple general purpose 
receivers. All MTK3329, MTK3339, MTK3333 (this one is GPS/Glonass) are 
claimed to has ±10 ns RMS PPS accuracy which is very promising result.
For
 new GPSDO
 design even with such good Mediatek chipsets available I would prefer 
dedicated modules from Trimble as Resolution SMT™ GG Multi-GNSS Timing 
Module: http://www.trimble.com/timing/pdf/022542-039A_Resolution_SMT_GG_DS_0412_US_LR.pdf 
They are build especially for timing purposes with TRAIM functionality (see datasheet).


My one cent about 2N2222 inverter used on PPS input between Adafruit receiver and 5V PIC input.
All
 precise timing are referred to the rising edge on the PPS output 
signal. So if unchanged in GPS or PIC software, the microcontroller will
 look for relatively slow rising edge on its input (rise time = multiply
 of input capacitance and pullup resistor). Events on the falling edge 
of PPS signals are not defined such well as raisng edge so uncontrolled 
jitter may occur between succesive falling PPS pulses. I would
 suggest to use two 74HCT series inverters in series with extra 470ohm 
5V pullup resistor on the PIC input istead of 2N2222 inverting stage. 
HCT logic works well with 3.3V CMOS outputs.


Best 73,
Michal
sp2iqw


>