[GPS_Standard] GPSstd_PLL testing V0.8

[Bob Stewart]

I've finally got some decent test equipment and the ability to do a phase plot on the software I'm working on.  I'll be doing plots on some of the stuff Dave and I have been working on, depending on how successful they actually turned out to be.  Obviously, any big failures will not make it to the "big screen".  It will take me several days to run all this, so it will be several days before the last one is up.  And, unless I'm badly mistaken, the last one will be the best.  The link is at the bottom of this post.

So, first up is a short plot of a run using only State Machine 1.  This is functionally equivalent to the Version 0.8 that I released some time ago.  So for now, I'm posting this, rather than doing a long run of the actual V0.8.  The curve on the top is the DAC voltage, and the one on the bottom is the interesting one, representing phase error.  Think of  "0" (on the right) as the zero phase error, "10" as +180degrees error, and "-10" as -180 degrees error.  

As you can see, at just after noon, the down-tick of the DAC appears to cause a phase lock.  By this, I mean that the phase angle always stays between the zero degrees and +180 degrees; so it's less than 180 degrees of total phase shift..  But, unfortunately, at 16:30, it penetrates the zero line for good, and it's clear that we were not strongly locked to phase as it continues on through -180 crashing through the top and going all the way to 0 degrees again.  In order to call it actually locked, the phase would need to at least stay between +180 and -180 at all times, though this would be an awfully poor condition of phase lock.  But, still and all, it's really not bad for a home-made GPSDO.

http://www.evoria.net/AE6RV/GPSstd_PLL/Plots/SM1.png