[GPS_Standard] Question about averaging mechanism

[Bert, VE2ZAZ]

Hello Everyone,

This is a very interesting topic to follow. It just shows that there is 
no perfect control system algorithm. By no mean would I say that my 
system is optimized in terms of algorithm. The good thing about it is 
that the platform allows to try out stuff. And I believe this is why I 
still get requests for the PIC and PCB seven years after publishing. 
People want to play with it and learn. Great!

When I designed the controller firmware, I went for a FLL for its 
simplicity of coding in assembly language. I did not see the need to 
track the phase as on a PLL. As long as, within the sampling period, I 
stayed within a reasonable frequency difference from reference, I would 
have met the objective. This turned out to be better than 1x10e-9. For 
that reason, I did not see any value in the accumulated (cumulative) 
error. This followed my approach in life: Over, let's move on and not 
look behind!... I am no expert in control systems. Like many, I studied 
the theory back at university and since then have seldom used the 
concepts. Hey, there is likely some more complex computation that could 
make use of it and improve the FLL. But it would probably be harder to 
code in 8-bit assembly language.

There is some value in displaying the cumulative error once the system 
is stabilized. If anything, it will show you where the OCXO is going and 
by how much. You can also look at the DAC value and that will give you a 
trend.

I have looked at how my Datum ExactTime 6000 (circa 2000) behaves in 
terms of frequency accuracy. Boy, oh boy their algorithm behaves in a 
complex manner! Impossible to find a pattern in the output frequency 
difference. On average, they do better than the ZAZ controller in terms 
of absolute frequency accuracy, but sometimes they veer off completely 
and unpredictably. Go figure!

Keep the discussion going! Thanks,

Bert, VE2ZAZ



On 07/21/2013 09:49 PM, Bob Stewart wrote:
> Dave,
>
> Here's a pastebin of some of today's test run of my latest PLL code.  I've added a field to the right which is the absolute value of the phase error count.  Take a look at the DAC numbers.  They almost seem to be oscillating on some very long period.  Does this ring any bells?  The power supply for the OCXO uses a 78LS12CT regulator regulating down from about 20 volts.  The power supply for the UT+ is a 7805 regulator regulating down from 10 volts, which also supplies Bert's board.  With a scope, I see about 50mv of high frequency noise on the power runs.  I don't have a DVM with enough digits to bother monitoring any voltage levels over the long term.
>
>
> http://pastebin.com/KfuwACHW
>
> Bob
> ______________________________________________________________
> GPS_Standard mailing list
> Home: http://mailman.qth.net/mailman/listinfo/gps_standard
> Help: http://mailman.qth.net/mmfaq.htm
> Post: mailto:GPS_Standard at mailman.qth.net
>
> This list hosted by: http://www.qsl.net
> Please help support this email list: http://www.qsl.net/donate.html
>
>