[GPS_Standard] Question about averaging mechanism

[Bob Stewart]

Dave,

Here's a pastebin of some of today's test run of my latest PLL code.  I've added a field to the right which is the absolute value of the phase error count.  Take a look at the DAC numbers.  They almost seem to be oscillating on some very long period.  Does this ring any bells?  The power supply for the OCXO uses a 78LS12CT regulator regulating down from about 20 volts.  The power supply for the UT+ is a 7805 regulator regulating down from 10 volts, which also supplies Bert's board.  With a scope, I see about 50mv of high frequency noise on the power runs.  I don't have a DVM with enough digits to bother monitoring any voltage levels over the long term.


http://pastebin.com/KfuwACHW

Bob