[GPS_Standard] GPS Standard with 26MHz VCTCXO

[Bert, VE2ZAZ]

Hi,

Indeed, the counter overflows 2441 times for each 16 second sample. The 
residual value that the FLL cares about is 26624.

Now, note that 16MHz is right at the fringe of the maximum frequency 
permitted on the counter input (1/60ns or 16.6MHz). The spec actually 
calls for a 30ns high and a 30ns low. If you take into account the rise 
and fall times, you may not meet this requirement. In other words, it 
may work well with a square wave, but not with a sine wave. Something to 
keep in mind...

Cheers,

Bert, VE2ZAZ

On 11/27/2012 12:31 AM, Dave Platt wrote:
>
>> Hi, I need a chip but stable 26MHz reference, so  I plan to use VE2ZAZ circuit with  a 26MHz VCTCXO (7x5mm module).
>> I noticed that if I feed 26MHz to thePIC, the 16bit counter will overflow. I don't want to use any dividers between the VCTCXO and the PIC.
>> So my idea was to change the 16sec period to 8sec and modify the 16bit counter value accordingly.
> As I understand it, the PIC's counter s lways giing to overflow, many times
> per sampling cycle, even at 10 MHz.  It has to... it can only count up to 65535, and
> at 10 MHz this is a small fraction of a second.
>
> The counter value at the time of the capture interrupt will be equal to the
> total number of oscillator ticks in the sampling period, modulo 65536.
>
>
> The FLL logic expects this.  What it is doing, is servoing the VCXO so that the
> final residue (remainder) is correct.
>
> So, all you should need to do is change the "expected" remainder value in
> the code to the right remainder.
>
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