[Elecraft] My K2 - Is this normal?

Fri Feb 14 15:52:01 2003

     I haven't been following the thread, but this reminds me of something
I ran into that might be related.  When first testing the PLL, I would hit
band+ to bring it to the top of the range, and it would immediately snap
back to the bottom (or vise versa -- can't recall :).  After about an hour
with a logic probe and scope, I had confirmed that the processor was
initiating the change!  Turned out that if the RIT value changed at all,
the test routine reset the PLL.  Turning the RIT to one end fixed it and I
was able to calibrate the voltage ranges.  I've been meaning to mention
this as a possible errata, but I never got 'round to verifying something
similar wasn't already in the manual and posting.


On Fri, 14 Feb 2003, Bob - AG5Q wrote:

>
> > > ... If all the external connections are good, maybe
> > > turning the pot end to end several times will make the internal wiper
> > > contact more stable. Otherwise, it might require new pots.
> >
> > Or it may be that the pot is sometimes set to a voltage which is a
> boundary
> > between bits on the ADC and absolutely nothing is amiss.
> >
>
> Leaving the pot sitting near the boundary of a bit change has a high
> probability of occuring.
> Since this spooky reading doesn't happen very often, I'm guessing there is
> some software filtering applied to the ADC value so only changes of more
> than one bit are considered significant.
>
> 73/ Bob - AG5Q
>
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