[DSP-10] PLL Tuneup Procedures

[Roger Hayward]

Greetings Group:

A while back, I asked the group if anyone had experimented with PLL 
diagnostics.  Since then, I have done some work in this area that I 
wanted to share.  This included an on-the-trail tutorial of PLLs by Wes, 
W7ZOI (far better than "books on tape"), as well as some great 
correspondence with Bob W7PUA on the procedures for computing 
synthesizer coefficients for U104.

I wrote a program (udiag3) to sweep the 126 MHz PLL across the entire 4 
MHz range, such that I could verify PLL lock in a test-bed, rather than 
from the dsp-10 dos application.  I also had great luck in getting both 
VCOs going by breaking the loop between PLL and VCO.  This turned the 
lock procedure into a one-evening slam-dunk.

Steve (N7HPR) has been hounding me to post this stuff, so here it is for 
your consumption:

    http://www.easystreet.com/~rhayward/dsp10/index.html

Please feel free to send constructive feedback.  Remember, personal 
feedback need-not be posted to the entire group :)  Thanks again to Wes 
& Bob for their fantastic mentoring skills.

Regards / 72.

    Roger ARS KA7EXM