[Test-Equipment] Need to shift pulse up 5V

Fri May 1 15:52:03 EDT 2015

 Barry,

The zero output would be minus the diode drop plus the saturation voltage(if it is in saturation, should be).
So, about -.4v depending on the transistor and current.
Most chips will tolerate up to about a diode drop negative, so you should be ok. 
If you are worried about it you can always add a diode in series and get it a little above zero.

Depending on what is the triggering edge of the divice the signal is coming from and what it
is going to, you may have to shift(+ +5v) or you may need to invert(* -1). 
But you got options for both ways.

Also what was not mentioned is what is the output and input impedance are, from the values mentioned,
it is assumed TTL levels, but there is a small chance that that is not the case. 

Jim,

On 05/01/15, Barry<n4buq at knology.net> wrote:

I see it now. I was thinking of it incorrectly. When the NPN is conducting, the two equal-value resistors form a voltage divider between +5V and -5V and when it is not conducting, that point is seeing +5V so - non-inverting.

One small point: doesn't the transistor's two diode-drops come into the equation effectively shifting that zero point when it is conducting?

I have a handful of 2N3904s so I will be trying this soon and, I agree - definitely a more elegant solution than a comparator.

BTW, these are strobe signals that set latches so not sure if an inverted clock would be okay but it might. With a non-inverted pulse, though, I won't worry about it.

Thanks again,
Barry - N4BUQ

----- Original Message -----
> From: "Mike Manes" <mrmanes at gmail.com>
> To: "Discussion of Electronic Test Equipment" <test-equipment at mailman.qth.net>
> Sent: Friday, May 1, 2015 12:10:44 PM
> Subject: Re: [Test-Equipment] Need to shift pulse up 5V
> 
> No, it doesn't invert the clock. When the emitter is pulled low by the
> -5V clock phase, the NPN turns on, and the collector voltage drops to
> zero. When the input clock goes high to 0V, then the NPN turns off and
> the collector voltage goes to +5 (or whatever +V bus it's fed from).
> 
> If the clock sig is just a freq reference, then inverting it wouldn't
> be no never-mind.
> 
> 73 de Mike W5VSI
> 
> On 5/1/15 10:23, David DiGiacomo wrote:
> > On Fri, May 1, 2015 at 10:13 AM, Barry <n4buq at knology.net> wrote:
> >> If I understand this correctly, when the clock is at -5V, the collector is
> >> at +5V and when the clock it at 0V, then the collector is at 0V. Is that
> >> correct? If so, then doesn't that invert my clock signal? If I'm
> >> thinking about it correctly (and I may be wrong), the comparator can be
> >> set to do either - depending on which way the inputs are connected,
> >> correct?
> >>
> >> I like the single transistor idea but if it inverts the signal, I'm not
> >> sure that's what I'm needing.
> >
> >
> > The common base circuit is non-inverting.
> > ______________________________________________________________
> > Test-Equipment mailing list
> > Home: http://mailman.qth.net/mailman/listinfo/test-equipment
> > Help: http://mailman.qth.net/mmfaq.htm
> > Post: mailto:Test-Equipment at mailman.qth.net
> >
> > This list hosted by: http://www.qsl.net
> > Please help support this email list: http://www.qsl.net/donate.html
> >
> ______________________________________________________________
> Test-Equipment mailing list
> Home: http://mailman.qth.net/mailman/listinfo/test-equipment
> Help: http://mailman.qth.net/mmfaq.htm
> Post: mailto:Test-Equipment at mailman.qth.net
> 
> This list hosted by: http://www.qsl.net
> Please help support this email list: http://www.qsl.net/donate.html
> 
______________________________________________________________
Test-Equipment mailing list
Home: http://mailman.qth.net/mailman/listinfo/test-equipment
Help: http://mailman.qth.net/mmfaq.htm
Post: mailto:Test-Equipment at mailman.qth.net

This list hosted by: http://www.qsl.net
Please help support this email list: http://www.qsl.net/donate.html