[Test-Equipment] PLL question

[windy10605@juno.com]

Since I received such an excellent and informative set of responses on my
previous flux removal question, thanks to all !  and Here is another one.

I'm looking at using one of the National LMX2306 PLL devices as a
frequency synthesizer for 6m (53Mhz) where channels at 100Khz 
spacing are specified. There are basically two PLL counters which feed
the phase comparison circuit to come up with the error signal. One
counter has the reference oscillator as input and the other has the
desired VCO as input. Why wouldn't you load the counters up with large
numbers to give a phase signal of 4Khz (for example) from both vs a phase
signal equal to the 100Khz channel spacing used (which National
suggests) ? Especially since this is for a transmitter ? The maximum
phase signal frequency is 10Mhz for this device. Is there a jitter
problem if I use 4Khz ? is there a slow time to lock ? I just don't
understand the reason for using the "channel spacing" as the phase signal
frequency. Help prevent the generating off frequency (channel) spurs ?

73 Kees K5BCQ