[Premium-Rx] [OT] PLL spurs?

[Brooke Clarke]

Hi:

I've recently been working with the ICS525 clock generator IC.  It's a 
PLL on a chip with parallel programmable dividers on the input, on the 
VCO and on the output.  For a little about it see:
http://www.pacificsites.com/~brooke/PRC68COM.shtml#BTSG
An on line calculator is at:
http://www.icst.com/calculators/ics525inputForm.html

When I set the dividers for 400 MHz output with a 16.6666 MHz input the 
spurs are spaced every 16.6 MHz either side of the output.  That's the 
same as the VCO input frequency.  But when the output is 51.0 MHz there 
are spurs every 1.375 kHz but the VCO input is 1.6666 MHz.

ICS says this is not suitable for use as a crystal replacement, probably 
for the reason above.  I'm trying to understand if there's a way to 
clean it up.  How can I calculate the spur seperation frequency?

Thanks,

Brooke Clarke



-- 
w/Java http://www.PRC68.com
w/o Java http://www.pacificsites.com/~brooke/PRC68COM.shtml
http://www.precisionclock.com