[Premium-Rx] RA1792 Synthesizer

[Andrew Holme]

Hi Group,

The principle of the RA1792 synthesiser is described in this RACAL patent from 1978:
 
http://l2.espacenet.com/espacenet/bnsviewer?CY=gb&LG=en&DB=EPD&PN=US4204174&ID=US+++4204174A1+I+
 
Regards,
Andrew Holme



----- Original Message ----- 
  From: Andrew Holme 
  To: premium-rx at ml.skirrow.org 
  Sent: Saturday, October 11, 2003 11:34 AM
  Subject: [Premium-Rx] RA1792 Synthesizer


  Hi Group,

  I've downloaded the RA1792 schematics from:
  http://kahuna.sdsu.edu/~mechtron/PremRxPage/racal_ra-1792.htm  

  I'm trying to understand the synthesizer (Module A7 fig. 8.7 & 8.8).

  Briefly, the VCO feeds a dual modulus pre-scaler followed by LSTTL dividers.  The divider output is compared to a 100 KHz reference by the phase comparator.  If the loop were closed at this point, we'd have a synthesizer with 100 KHz steps.
   
  To get 10 Hz steps, the phase error is summed with the output of a digital to analogue converter, which generates a dynamic correction.  An accumulator comprising registers and a binary adder computes the 8-bit digital input.
   
  I'm having trouble understanding the circuitry around op-amp U33B, which generates the reference voltage input for the DAC (U23).

  Here are a few random observations:
  The phase error/correction are summed at the junction of C78, C80 and R60
  The (positive) pulse at the cathode of CR9 is equal to the divider output i.e. short duty cycle.
  C72 charges through Q6 during this (short) pulse.
  The emitters of current-sources Q6, Q7 and Q8 are held at roughly the same voltage.

  Can anyone give me a clue?
   
  Regards,
  Andrew Holme. 



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