[Premium-Rx] RA1792 Synthesizer

[Carcia, Frank A. HS]

    Hi All,
    Interesting questions. I played with the 6830 synthesizer this weekend
and found a simple way of adjusting the analog compensation pot R11. I ran
the ARRL method of measuring phase noise with the 300 hz. filter selected. I
went 4 kHz. off frequency and ran the signal generator up until there was
deflection on the RMS meter and noise coming out of the speaker.
   I adjusted the R11 pot for minimum noise and deflection on the RMS meter.
There was a nice 6 to 8 db null testing 4
different modules. I now have 1 problem. One module is 10 dB better than the
other three. It has some extra parts on the loop filter board. I moved the
board to another module and the performance followed the loop filter board.
I am presently populating
another board to see if I can duplicate the performance. This is the 4100516
module. The older 118 module works the same as
the 516 without the extra loop parts. The 6830 has the Racal LSI fractional
controller while the older units used discrete logic.
The extra parts are 2 2n2907s, 1 CA3046, 1 7808, 14 resistors, two caps. I
wonder if anybody has a schematic of this function in
any Racal model? I will report when I figure out why this is happening. fc 

-----Original Message-----
From: Andrew Holme [mailto:andrew at holmea.demon.co.uk]
Sent: Saturday, October 11, 2003 6:35 AM
To: premium-rx at ml.skirrow.org
Subject: [Premium-Rx] RA1792 Synthesizer


Hi Group,
 
I've downloaded the RA1792 schematics from:
http://kahuna.sdsu.edu/~mechtron/PremRxPage/racal_ra-1792.htm
<http://kahuna.sdsu.edu/~mechtron/PremRxPage/racal_ra-1792.htm>   
 
I'm trying to understand the synthesizer (Module A7 fig. 8.7 & 8.8).
 
Briefly, the VCO feeds a dual modulus pre-scaler followed by LSTTL dividers.
The divider output is compared to a 100 KHz reference by the phase
comparator.  If the loop were closed at this point, we'd have a synthesizer
with 100 KHz steps.
 
To get 10 Hz steps, the phase error is summed with the output of a digital
to analogue converter, which generates a dynamic correction.  An accumulator
comprising registers and a binary adder computes the 8-bit digital input.
 
I'm having trouble understanding the circuitry around op-amp U33B, which
generates the reference voltage input for the DAC (U23).
 
Here are a few random observations:
The phase error/correction are summed at the junction of C78, C80 and R60
The (positive) pulse at the cathode of CR9 is equal to the divider output
i.e. short duty cycle.
C72 charges through Q6 during this (short) pulse.
The emitters of current-sources Q6, Q7 and Q8 are held at roughly the same
voltage.
 
Can anyone give me a clue?
 
Regards,
Andrew Holme. 


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