[Lowfer] Lowfer KE

[John Hamer]

I Believe he has the capacitors on the oscillator and they are just not on
the schematic he posted.  I went through datasheet with him over the summer
and calculated the proper capacitor values.

Regards
John Hamer
Lowfer JH

On Sun, Nov 22, 2020, 9:28 AM KA4SEY <ka4sey at gmail.com> wrote:

> Thank you John, I will add those capacitors on in the future and make any
> other changes. Like I said I'm going to try another configuration with the
> coil today to see if it will do any better. I will hopefully find an
> ammeter which would help me a lot. Thanks againKaseySent from my Verizon,
> Samsung Galaxy smartphone
> -------- Original message --------From: J D <listread at lwca.org> Date:
> 11/22/20  2:27 AM  (GMT-05:00) To: lowfer at mailman.qth.net Subject: Re:
> [Lowfer] Lowfer KE Kasey, it would appear from your schematic that a few
> components may be missing, thereby preventing your oscillator from being as
> stable as it needs to be. This same situation is found in a commercially
> made sorta-kit rig for 22 meters, and beacons using it there can often be
> identified by their tendency to wander or even outright jump around in
> frequency from day to day.A Pierce oscillator needs capacitance from both
> legs of the crystal to ground as part of a phase shift network. There is
> stray capacitance present, of course, without which it would not oscillate
> at all; but that is neither of sufficient magnitude nor stability to ensure
> reliable oscillation at the design frequency of the crystal. A good
> starting value for capacitors for a typical 3 MHz parallel resonant crystal
> would be 27 pF each.In addition, there n
>  eeds to be a series resistor between pin 10 and the crystal. It serves
> three functions that each affect frequency stability to a certain extent:
> it isolates the crystal somewhat from the complex impedance of the gate
> output, it limits current and thereby power dissipation in the crystal, and
> it is part of the phase delay network. As a rough first approximation, I'd
> suggest 1 K, maybe as high as 2.2 K.Finally, the shunt resistance across
> the crystal could be a little higher in value for 3 MHz operation, such as
> 3.3 M to 4.7 M. It's not terribly critical, but it is preferable to operate
> it with as high a value as will allow for reliable startup. Lowering the
> operating Q of the crystal with a low parallel resistance could allow a
> crystal to jump too easily between primary resonance and any secondary
> resonance modes it may have.These comments are some basic rule of thumb
> guidance. For more detailed treatment of Pierce oscillators implemented
> with logic gates, I believe Crystek s
>  till offers this article:
> https://www.crystek.com/documents/appnotes/pierce-gateintroduction.pdfJohn
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