[Lowfer] JFET (J310) Biasing

[Clive S Carver]

Hello John JD, Tom, John W1TAG and Mike

Thank you for your replies.

The reason I asked the question was that I have recently purchased off eBay
a couple of rather nicely made, double-sided pcb's with
through-hole-plating, solder resist and screen printing for PA0RDT based
e-probe.

I use a PA0RDT e-probe to good effect, however from the circuit could see
that it was not optimum for VLF. Value of coupling capacitors and feed
choke.  I did modify my bias-T to help improve VLF response. I had purchased
e-probe and bias-T from Roelof Bakker PA0RDT in 2007 and his construction is
superb. I felt guilty taking a soldering iron to it, but reminded myself
that English Electric Lightnings and Nimrods had survived my soldering, so
went ahead. (I worked for the UK MoD as a civilian in the late 60s/70s) 

So my plan was to build a couple of PA0RDT e-probes myself and see if I
could improve VLF reception, by using higher value coupling capacitors and
feed choke.

73's

Clive
GW4EYO


From: Lowfer [mailto:lowfer-bounces at mailman.qth.net] On Behalf Of Clive S
Carver
Sent: 28 June 2014 18:20
To: Lowfer at mailman.qth.net
Subject: [Lowfer] JFET (J310) Biasing


I am curious of the pro's and con's of three different ways of biasing a
J310 for use as an e-Probe front end stage.

1. For example, the PA0RDT mini-whip uses two 1Mohm resistors in a potential
divider across the +12ve to ground supply, with a third 1Mohm resistor
between the potential divider mid-point and the J310 gate.

2. Some designs omit the third 1Mohm resistor referred to above, and connect
the potential divider mid-point directly to the J310 gate.

3. I have also come across a design where there is a single 1Mohm resistor
between the +12ve rail and the J310 gate.

So, what are the advantages/disadvantages in the three methods (besides
using less 1Mohm resistors!).

73's

Clive
GW4EYO


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