[GreenKeys] Diddle, Real Metal, & Indeterminate Line Length

[Veenstra, Lester]

Agree, an actual 1.0 stop bit with real mechanical machines defeats
their mechanical design. I suspect the introduction of 1.5 and 2.0 stops
are reflections of reality that, at some point in the system, there will
be an electronic clock that will have a trouble synthesizing a bit
duration of 0.42.

Lester Veenstra
Senior Engineering Program Manager
Intelsat General
6550 Rock Springs Drive, Suite 450
Bethesda Maryland, 20817
+1-301-571-1212
e-mail: lester.veenstra at intelsatgeneral.com
 

-----Original Message-----
From: Bob Camp [mailto:ham at cq.nu] 
Sent: Friday, February 25, 2005 9:16 AM
To: Veenstra, Lester; Greenkeys
Cc: Jerry
Subject: Re: [GreenKeys] Diddle, Real Metal, & Indeterminate Line Length

Hi

You are correct at least as far as the machines I have really dug into 
(15's). The mechanical felt pad clutch engages at the end of a 1.0 
length stop pulse. The only problem with this is that it (as least from 
20 year old memory) is a full 1.0 length pulse. If the sending machine 
is running just a bit fast the receiving machine will fall out of 
synchronization every so often.

As far as I can see there is no advantage to diddle on a mechanical 
TTY. There certainly is an advantage on certain types of TU's but not 
on the TTY it's self. If anything diddle wears out the machine a bit 
faster.

The biggest problem I see with "synthetic sync" operation using diddle 
is that you do not have a defined stop bit length. Normal clock and 
data recovery circuits rely very much on the fact that they know 
exactly what they are looking for. Each weird stop bit length (1.31, 
1.42, 1.5) effectively is a different clock rate you have to watch for. 
I have never seen a sync system that uses odd width pulses in the bit 
stream.

This isn't to say you can't watch for all the possible rates and guess 
which one is being used. The issue is that you can guess wrong if you 
have  three closely spaced stop pulse widths. If you really want to go 
wild you can always go to a Veterbi decoder and do convolutional guess 
work until you run out of CPU clock cycles. I suspect that at 45 baud 
that a lot of of bits (> 2 characters) . It would still work better if 
you knew the stop pulse width ahead of time since you would have fewer 
buckets to examine and less chance of error.

We're getting a bit far afield from my original intention here which 
was simply to caution about the use of 1.0 length stop bits if there's 
a mechanical TTY on the other end ...

	Take Care!

		Bob Camp
		KB8TQ



On Feb 25, 2005, at 8:11 AM, Veenstra, Lester wrote:

> Actually, I believe you will find that, with respect to receive, the
> mechanical units are actually set up with a 1.0 stop. The additional
> stop time is the key to async operation. That is, a format that allows
> the receiver to resynchronize one per character cycle with the stop
> start transition. The elongated stop bit serves to allow machines with
> minor speed variations to be at a common state and ready to start at 
> the
> next character receipt.
>
> " machines with minor speed variations" : machines that are close 
> enough
> in speed that, over the length of one character, they are still 
> sampling
> the incoming bits at an time the signal not in transition.
>
> "Async Operation":  In this perspective with mechanical machines, 
> diddle
> generation has no real effect on the error performance, and it's
> perceived benefit is probably more psychological.  While not having
the
> machine at rest waiting for the next real stop start transition, as a
> consequence of a diddle character receipt, means that a burst of noise
> is not going to act as a false start, the burst of noise will still
> generate an error by corrupting the diddle character.
>
> Sync Operation is a better way to operate, but this means that you are
> using a sync receiver that has an accurate enough clock to preserve
bit
> timing without the need to correct the "internal (mechanical) clock 
> with
> an artificial stop start transition added to the 5 bit character 
> stream.
> An example of a sync system is TOR/TOM (AMTOR)(476-2) where the
> transmitter and receiver have high accuracy clocks to begin with and
> receiver bit timing (phasing) is accomplished by averaging the errors 
> in
> timing observed over a number of bit transitions. The two bits gained 
> by
> not needing a stop start transition are then used for a two bit 
> checksum
> (FEC) for error detection, significantly improving the character error
> performance for a given bit error rate by introducing the ability to
> operate with ARQ.
>
> Now a nominal async system operated with diddle, and received by an
cpu
> based decoder can improve error performance by two methods.
>
> 	First, the receive clock can be generated by a synch process
> where the timing is derived by an average (filter) process that is not
> dependent on the stop start transition. That is to say, a burst of 
> noise
> (one bit error) will not cause an error condition that will passably
> corrupt two characters (ten bits essentially errored).
>
> 	Second, a CPU vice mechanical receiver can perform filtering
> over the entire bit time. That is, use all the information available
> with respect to the state of a bit. In contrast a mechanical receiver
> only samples the receive waveform (the 60/20 ma loop current) for a
> fraction of the bit time. The selector mechanism adjustment is in fact
> an attempt to get this mechanical sample point in the middle of the
bit
> over the entire 5 bits of a character.
>
> (For more see TELEGRAPH AND DATA TRANSMISSION OVER SHORT WAVE RADIO
> LINKS by Lothar Wiesner, Seimens Aktiengesellschaft, Hayden & Son LTD.
> ISBNs  3-8009-1211-2,  3-8009-1232-5, 0-85501-243-9)
>
>
> Lester Veenstra
> Senior Engineering Program Manager
> Intelsat General
> 6550 Rock Springs Drive, Suite 450
> Bethesda Maryland, 20817
> +1-301-571-1212
> e-mail: lester.veenstra at intelsatgeneral.com
>
>
> -----Original Message-----
> From: greenkeys-bounces at mailman.qth.net
> [mailto:greenkeys-bounces at mailman.qth.net] On Behalf Of Bob Camp
> Sent: Thursday, February 24, 2005 6:35 PM
> To: Jerry; Greenkeys
> Subject: Re: [GreenKeys] Diddle, Real Metal, & Indeterminate Line 
> Length
>
> Hi
>
> Diddle diddle diddle ....
>
> There is one minor problem with diddle. It has to do with the pesky
> stop bit problem. These days we more or less stick with 1 or 2 stop
> bits in ASCII code. Rarely if ever will you see an 8 bit guy talk
about
> 1.5 stop bits. Oddly enough a lot of mechanical gear was set up for a
> stop bit length of 1.42.
> ...............
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