[GPS_Standard] DAC/EFC voltage dividers and thermal drift

[Bob Stewart]

One of the limitations of Bert's board is that is only has 14 bits in the DAC.  This means that we are limited in precision to 1 part in 16384 times the range of our OCXO.  So, for example, with an OCXO having a range of 7.5Hz, we can't make any adjustment smaller than .00046 Hz or about 46 PPT.

We can improve on this by putting a voltage divider in the EFC line to the OCXO, as I think some of you have done.  I wanted to use the simplest possible circuit to accomplish this, so I started with two 10K ohm 25 turn pots.  After I got the adjustments to work, I bought standard value fixed resistors and wound up with this.  http://www.evoria.net/AE6RV/GPSstd_PLL/EFC%20Divider/EFC.png

I had originally thought that R1 and R2 formed the EFC voltage divider, with R3, R4, and R5 forming another divider to
 re-center the divided EFC.  But after looking at the circuit, I saw that this was wrong.  In fact, both dividers share the bottom leg of R4 and the value of R5.  To get the actual division factor being applied to the EFC, we need to take all these into account.  We can make a guess that we're using half of R4, and we wind up with (R1 + R2 + R4/2 + R5) / (R2 + R4/2 + R5), or about 3.4:1.  We would like to reduce the range of our 7.5Hz OCXO to 2Hz, so we need a ratio of 3.75:1.  So, it's not exact, but it's close enough.

But what would be even better is if we could reduce the affects of R4 and R5.  That can be done by simply using about 1/10th of the values of R3, R4, and R5 in our actual correction divider.  We'd also need to change the value of R2, as well, to 6.8K.  This gives us R1=20K, R2=6.8K, R3=680, R4=100, R5=390.  And the resultant ratio is about 3.76, which is very close to the 3.75
 that we wanted.  http://www.evoria.net/AE6RV/GPSstd_PLL/EFC%20Divider/EFC2.png  I haven't tried these values yet.

If you also follow time nuts, you've seen my thread on EFC dividers and temperature drift.  Dave had a lot of problems with drift, but it never seemed to affect me until I installed this divider.  I've ordered some low temperature coefficient resistors to replace the ones mentioned above.  While waiting for them, after some experimentation, I wound up putting my GPSDO on the floor.  My house is on a slab, so the floor is a pretty large heat sink.  The results of the divider and moving it to the floor are better than I could have hoped.

Here is the link to a plot of 24 hours using the divider with the GPDSO on the floor:  www.evoria.net/AE6RV/GPSstd_PLL/EFC%20Divider/2.3.24hr.png    Notice that there are only 4 DAC changes.  The phase error plot is in green as always, bounded by +10 and -10 on the right..  The red line is the error in parts per trillion as indicated on the right label of the plot.  The red line really should just be 4 dots, but I already have this plotted.  The DAC is the green/blue/orange line.

I will be putting the low temp coeff resistors in in the next week or two and report back.

Bob - AE6RV