[GPS_Standard] My PLL version's status and a hardware change

[Bob Stewart]

Hi Bert,

My mistake, I'm afraid.  Somehow while testing with the 8MHz clock, I had convinced myself that stopping interrupts to write to the EEPROM was fouling up the count.  But, I just tried it with the 40MHz clock, and I cannot make it happen.  I don't know what happened with your code when you were trying to use T1CKI for the clock.  I have not had a problem with lost or extra counts that I can detect.  Were you running HSPLL and 40MHz, or just HS and 10MHz?  

I have run your chip from time to time in the past couple of days, and yours  seems to want to resolve to the same answer, or thereabouts, as mine.  It's hard to be absolutely sure, because of, I think, temperature differences during the day.  And probably the fact that I haven't left yours running for a really extended period of time with this OCXO.  Another issue is that to get to a really small resolution, yours has to be set to a very long sample count.  With mine, there is no set sample count - the time between updates just gets longer as the DAC gets closer to best solution - so convergence probably comes faster.

I hope to be ready to let someone test my code soon, if there is any interest.  It still has a lot of dumb debugging comments and the LOS testing/Holdover is still disabled, but the PLL is working; as is most everything else.  If there's no interest, I'll probably have to get a rubidium oscillator, as I have nothing here with any useful accuracy other than this GPSDO.  I've been depending on DAC comparisons, but my OCXO took a burp yesterday and the DAC setting at lock has changed for both my code and yours.

Bob





>________________________________
> From: "Bert, VE2ZAZ" <ve2zaz at sympatico.ca>
>To: Bob Stewart <bob at evoria.net> 
>Sent: Sunday, September 1, 2013 5:35 AM
>Subject: Re: [GPS_Standard] My PLL version's status and a hardware change
> 
>
>
>Hi Bob, 
>
>I am sorry for taking so long answering your question. I do not
    write the DAC value to EEPROM while changing the DAC. I first change
    the DAC and then start an EEPROM writing cycle.
>
>I could never really figure out why it did not converge with a
    common clock, but I concluded that it must have been the CCP
    registers that don't like to be latch in sync with the CPU core
    clock. I guess the counter value capture and transfer to CCPR1 has
    the CPU clock involved in some way...
>
>Cheers,
>
>Bert, VE2ZAZ
>
>