[GPS_Standard] Fwd: Re: GPSstd_PLL testing: V0.13 with an improved State Machine 2
Bob Stewart
bob at evoria.net
Fri Nov 15 09:18:47 EST 2013
Hi Michal,
My next release will have a compiler switch to choose either rising or falling edge. And, yeah, I thought of using a real DAC, but my design goal for my software was no hardware changes other than jumpering pin 9 to pin 11 on the PIC to get the 40MHz clock rate.
Bob
>________________________________
> From: Michal <michal at e2000.gdynia.pl>
>To: bob at evoria.net
>Sent: Friday, November 15, 2013 2:12 AM
>Subject: Fwd: Re: [GPS_Standard] GPSstd_PLL testing: V0.13 with an improved State Machine 2
>
>
>
>Hi Bob,
>
>Yes, the falling edge of the PN2222 inverted signal will be also
good if handled by S/W instead of normally used rising edge. In
similar inverter circuits I have added a small 22-47pF capacitor
parallel to the base resistor to further speed-up the switching
time. A good practise is also to use relatively small 330-470ohm
pullup resistors in the collector (but it helps when the transistor
is being switched off).
>
>It will be good to leave the control the PPS edge selection to the
user either by configuration software or by monitoring the state of
any unused pin (for example: left open = H = rising edge, pulled to
GND = L = falling edge).
>
>
>The last idea I think it is worth to consider is the use of 14-16-bit DAC instead of PWM circuit. In my commercial I'm applyig the DAC8562 chip from TI (easily available from e.g.. Digikey). For this design single channel DAC8560 seems to be perfect solution. With voltage output, low power, serial input and internal reference it looks like a trouble-free design. For those who needs budget solution the PWM will remain :-)
>
>Best 73,
>Michal
>sp2iqw
>
>
>
>-- Treść oryginalnej wiadomości --
>Temat: Re: [GPS_Standard] GPSstd_PLL testing: V0.13 with an improved State Machine 2
>Data: Thu, 14 Nov 2013 16:03:19 -0800 (PST)
>Nadawca: Bob Stewart <bob at evoria.net>
>Odpowiedź-Do: Bob Stewart <bob at evoria.net>
>Adresat: SP2IQW <michal at e2000.gdynia.pl>
>
>
>Hi Michal,
>
>Regarding the result of the PN2222A inversion, wouldn't it be
enough just to change the code to monitor the falling edge
instead of the rising edge? I haven't done that yet. I think
on my next compile I'll give it a shot.
>
>Bob
>
>
>
>
>
>
>>________________________________
>> From: SP2IQW <michal at e2000.gdynia.pl>
>>To: gps_standard at mailman.qth.net
>>Cc: Bob Stewart <bob at evoria.net>
>>Sent: Thursday, November 14, 2013 5:44 PM
>>Subject: Re: [GPS_Standard] GPSstd_PLL testing: V0.13 with an improved State Machine 2
>>
>>
>>Hi Bob and All,
>>
>>I'm carefully observing your software work on
improving Berts's GPSDO.
>>Few years ago I have build VE2ZAZ GPSDO with some
hardware rework. To eliminate jitter caused by noisy
and not so stable 5V PS line I have added uA723 based
5V voltage regulator supplying only CMOS buffer
(non-inverting) on the PWM output.
>>
>>As per GPS, your choice to use MTK-chipset means
current "state of art" within simple general purpose
receivers. All MTK3329, MTK3339, MTK3333 (this one is
GPS/Glonass) are claimed to has ±10 ns RMS PPS
accuracy which is very promising result.
>>For new GPSDO design even with such good Mediatek
chipsets available I would prefer dedicated modules
from Trimble as Resolution SMT™ GG Multi-GNSS Timing
Module: http://www.trimble.com/timing/pdf/022542-039A_Resolution_SMT_GG_DS_0412_US_LR.pdf
>>They are build especially for timing purposes with
TRAIM functionality (see datasheet).
>>
>>
>>My one cent about 2N2222 inverter used on PPS input
between Adafruit receiver and 5V PIC input.
>>All precise timing are referred to the rising edge on
the PPS output signal. So if unchanged in GPS or PIC
software, the microcontroller will look for relatively
slow rising edge on its input (rise time = multiply of
input capacitance and pullup resistor). Events on the
falling edge of PPS signals are not defined such well
as raisng edge so uncontrolled jitter may occur
between succesive falling PPS pulses. I would suggest
to use two 74HCT series inverters in series with extra
470ohm 5V pullup resistor on the PIC input istead of
2N2222 inverting stage. HCT logic works well with 3.3V
CMOS outputs.
>>
>>
>>Best 73,
>>Michal
>>sp2iqw
>>
>>
>>
>>W dniu 2013-11-13 21:55, Bob Stewart pisze:
>>> Here I am running a test on what is essentially
an upgraded Version 0.13 with a slightly improved
State Machine 2. Jim had asked me to run a long test
of the one with just State Machine 1 that I posted
previously, but this will have to suffice for now.
The performance should be more or less the same as
V0.8 since the Adafruit receiver doesn't have the wild
phase jumps on the 1PPS signal that come from the UT+
that I was trying to tame. I've decided to run this
until at least tomorrow morning. So I'll update it
then.
>>>
>>> http://www.evoria.net/AE6RV/GPSstd_PLL/Plots/SM1SM2.30hrs.png
>>>
>>> Just as a reminder, this is with using an
Adafruit Ultimate Breakout GPS Receiver with the
antenna near the peak of the attic. There is a
PN2222A serving as an amp/inverter in the 1PPS line,
as the Adafruit doesn't have enough drive to provide a
reliable TTL signal to the 18F2220.
>>>
>>> For test equipment, I am using a Prologix
Ethernet GPIB adapter and an HP 5334B to provide the
phase timing. The 10MHz signal from Bert's board is
serving as the timebase for the 5334B. The 1PPS
signal goes to the A Channel and the 10MHz output from
Bert's board (different port from timebase) is going
to the B Channel. The mode is TI A->B, which
measures the time interval from the rising edge of the
pulse on Channel A (1PPS) to the rising edge of the
next pulse on Channel B (10MHz from Bert's board).
The monitoring software is home-grown.
>>>
>>>
>>> Bob - AE6RV
>>>
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