[GPS_Standard] My PLL version's status and a hardware change

[Bob Stewart]

As I've continued to make changes to Bert's code to turn it into a Phase Locked Loop, I have wondered why the tick to tick (PPS) phase change has been so high.  I have been seeing  +/- 5 clocks or even more (of the 10MHz clock) from tick to tick.  IOW, one second might show a clock count of 9683 (I'm checking every second) and the next might be 95FD.   I have been speculating for some time that it might be related to the 125ns uncertainty that an 8MHz clock gives.  Yesterday I finally jumpered pin 9 to pin 11 on the PIC and put all doubts to rest.  After making the changes to my code to run it in HSPLL mode (40 MHz locked to the 10MHz oscillator), as well as changing the baud rate divisor, I am seeing the phase switch that I was expecting for a properly locked PLL with an uncertainty of 25ns: mostly no change from tick to tick, and when there is, a +1 count followed pretty quickly by a -1 count, or vice versa, depending on the UT+ sawtooth.

At some time in the future I'll probably make the changes to Bert's FLL code and see what difference, if any, it makes.  But for now, I'll continue with the next steps of my PLL version.  It's going to be some time yet before I'll be willing to let anyone see it.

Bob - AE6RV