[Elecraft] Power level displays when K2 VFO turns?

[VR2BrettGraham]

N0SS added:

>Just a gut feeling, but I suspect it's an AUX BUS timing issue, where 
>there might (periodically) be a collision between two devices both wanting 
>to send data at the same time. Probably not worth attempting to fix in 
>firmware.

That's what I first thought - but isn't AUX BUS inter-board, not intra-board?

AUX BUS goes to the front panel board, but goes nowhere past J1.  All these 
knobs
are on the front panel board, not the control board.  No chance for collisions.

I wasn't really with it enough at 03:00 when Tom's post came in (woke from 
what was
supposed to be a short nap before Letterman due to mosquito bites), but now 
that
I'm awake enough to read I see the keyer speed, power & RIT pots share a line
called VPOTS & that is one transistor away from the DN line on the mic 
connector,
all of which is pulled up to the 5A rail by 10k ohms.

My vote is on the control board stepping on itself somehow as it's reading the
various front panel bits.  Having been able to make this happen 
consistently for the
first time as noted after NA8M's post, I was thinking the only variable is 
the CPU
clock - it's the same code reading the front panel, the only thing changing 
over time
is time by way of what isn't that much change in the CPU clock 
frequency.  What I
am certain of is that since I'm not the only one seeing it, something like 
encoder
pulses being seen somewhere they shouldn't due to semi-conductive flux 
residue on
the board or something is unlikely.

A welcome diversion from what I should be doing now - figuring out why a few
hundred kb/s of Thai & Chinese subtitling within a 50 Mb/s DVB transport
stream is fumbled by one chip that's demuxing, decrypting, reconstituting &
regurgitating several more Mb/s of service components at the same time.  A very
welcome diversion...

73, VR2BrettGraham