[DSP-10] U107 Voltages

Sat, 6 Mar 2004 19:13:03 -0700

Hello Jiro,

The problem comes from the level shifters on the KDSP10 board (the
PI5C3245S).  Level shifting takes time, and you see this in your o'scope
traces as sloping traces on the Serial Clock (FL2) and Serial Data (FL0).

My solution was to use an additional 74HC14 DIP and piggy back it on top of
U3 on the KDSP10 board.  Bend pins 1 through 6 and 8 through 13 pins
straight out from the package.  Be careful not to stress the pin too much as
you bend it, they may break.  Clip off the narrow part of the pin and leave
the thick part of the pin.  Allow the power (pin 14) and ground (pin 7) pins
to stay the same, hanging down.  Piggy back the 74HC14 to the top of U3 by
soldering the power (pin 14) and ground (pin 7) pins to the same on U3.
This provides power and groud to the top 74HC14.

Connect a wire from P2-4 (FL2) on the KDSP10 to pin 13 of the piggy back
74HC14.  Connect a wire from pin 12 to 11.  Connect a wire from pin 10 to
the through hole capacitor for FL2.

Connect a wire from P2-3 (FL0) on the KDSP10 to pin 1 of the piggy back
74HC14.  Connect a wire from pin 2 to 3.  Connect a wire from pin 4 to the
through hole capacitor for FL0.

I appoligize for only words to describe the above solution.  If you like, I
can take some photos and post them to a web page.

Please let us know if this helps solve your problem.

73,

- Steve, N7HPR
 ([email protected])

> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]]On Behalf Of Yamamoto Jiro
> Sent: Thursday, March 04, 2004 5:10 AM
> To: [email protected]
> Subject: Re: [DSP-10] U107 Voltages
>
>
> I took traces of serial bus signals for both cases using with my scope
> (analog and logical). I published the result at
> <http://bagdad-cafe.homedns.org/dsp10/traces.html>. It seems to be
> sensitive to some factors (clock frequency, signal waveform or
> something else???) whether in cascading U107 the serial data is high
> level or not when the serial clock rises. Is it possible to think that
> this causes the different result...
>
> Regards,
> Jiro JQ2LMG
>
> On Thu, 26 Feb 2004 20:08:19 +0900, Yamamoto Jiro wrote:
> > Thanks Bob,
> >
> >>  It seems puzzling why the UDIAG2.EXE and UHFA driven programming
> >>  would be different. When you run UHFA , do you get the incorrect U108
> >>  outputs, or is it just U107?  The programming from UHFA consists of
> >>  sending the value for U107, U108 and the 126 MHz PLL to the DSP and
> >>  the actual programming is done as part of the interrupt processing.
> >>  With UDIAG2 it is much simpler, but the end results should be the
> >>  same !!
> >
> > When UHFA.EXE is running, U108 is correct, which voltage outputs are
> > exactly same as when UDIAG2.EXE. Only U107 voltages are offset by 1.
> > Very strange...
> >
> >>   When I get a chance, I will look at he differences between the two
> >>  programs. For now, it would be helpful to see that the U108 voltage
> >>  outputs are also offset by 1 position.
> >>
> >>  Your other IC voltages seem OK, although the Lock Detect is obviously
> >>  unlocked, as you have observed. The first step would seem to be
> >>  getting the serial programming to work.
> >
> > Ok, I hope I could get it to work.
> >
> > - Jiro, JQ2LMG
> > _______________________________________________
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> >
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