[DSP-10] PLL Problems

[Doug Bade]

If the VCO is not the problem, you may be finding what some of us have. The 
Clock from the DSP into the shift register has a poor rising edge pulse, 
causing erratic loading of the PLL data. If you re-route the clock into the 
DSP-10 through a buffer IC "dead bug " mounted, at least temporarily, and 
clean up the rising edge of the pulse. The clock seesm to get distorted in 
some cases, as it come through the feed through capacitor. The ramping 
leading edge triggers erratically before the data is steady, or maybe false 
trigger multiple times. 2 NAND gates or 2 inverters will work, 74HC style 
parts or equivalent...

Maybe this will be your problem too.
Doug KB8GVQ




At 10:28 AM 1/11/2004, you wrote:
>I don't know how and why it happen. Sometimes it's able to lock at the 
>range 100MHz-105MHz, sometimes it's not. I did wait for few seconds to few 
>minutes after reset/power on the EZ-Kit before reloading any software.
>
>Did anyone face this before?
>
>Regards,
>Tan Teik Chuan
>
>_________________________________________________________________
>Are you in love? Find a date on MSN Personals http://match.msn.com.my/
>
>_______________________________________________
>DSP-10 mailing list
>DSP-10@mailman.qth.net
>http://mailman.qth.net/mailman/listinfo/dsp-10