Hello Jiro,
It seems puzzling why the UDIAG2.EXE and UHFA driven programming would be
different. When you run UHFA , do you get the incorrect U108 outputs, or is
it just U107? The programming from UHFA consists of sending the value for
U107, U108 and the 126 MHz PLL to the DSP and the actual programming is
done as part of the interrupt processing. With UDIAG2 it is much simpler,
but the end results should be the same !!
When I get a chance, I will look at he differences between the two
programs. For now, it would be helpful to see that the U108 voltage outputs
are also offset by 1 position.
Your other IC voltages seem OK, although the Lock Detect is obviously
unlocked, as you have observed. The first step would seem to be getting the
serial programming to work.
73,
Bob W7PUA
At 09:42 PM 2/22/2004, you wrote:
>Hello Bob,
>> > What voltages do you see on U108 QA to QH? In receive, I believe
> > only QC (U108-2) should be 5V and the others 0V. What success are
> > you seeing with programming the PLL frequency synthesizers?
>>As to the U108 voltages, I observed that only pin 2 was 5V and other
>pins were 0V. They all are same as you pointed out. Both of the PLLs
>are not working. I tried your PLL diagnostic program, udiag2.exe, and
>the red LED did not go out. It was keeping on. After checking the
>U104-7 and U7-11 voltages, I found that both of the PLLs was not
>locked. Here are the observed voltages after loading udiag2.exe;
>> U107-15 0 V
> U107-1 0 V
> U107-2 0 V
> U107-3 4.7 V
> U107-4 0 V
> U107-5 0 V
> U107-6 0 V
> U107-7 4.7 V
>> U108-15 0 V
> U108-1 0 V
> U108-2 5 V
> U108-3 0 V
> U108-4 0 V
> U108-5 0 V
> U108-6 0 V
> U108-7 0 V
>> R110 1.7 V
> R59 1.4 V
>> U104-3 5.0 V
> U104-4 5.0 V
> U7-16 4.9 V
> Across R44 0.13 V
> U105-1 In 1.5 V
> U105-3 Out 2.0 V
> U106-1 In 1.4 V
> U106-3 Out 3.8 V
> U8-1 In 1.1 V
> U8-3 Out 2.9 V
> U9-1 In 2.1 V
> U9-3 In 3.5 V
> U104-7 2 V
> U7-11 2.4 V
>> D1-A1 0.79V
> D2-A1 0.8V
>>This time (udiag2.exe) U107 seems to work properly while it does not
>under running UHF3 and UHFA!!! Anyway I need to investigate the PLL
>problem more. I am going to do it later with my new scope!
>>- Jiro, JQ2LMG
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