[DSP-10] KDSP10 Info

Thu, 22 May 2003 10:33:25 +0100

Hi Doug,

You have one inverter available at U110 pin 3 and 4, but it is only one
that is why I changed the DSP code.
But if you don't want to mess up with the dsp code you have to
do as you did, with 2 inverters.

Or I can send you the ready made binary, to program an eprom
with this line changed... also will never get the anoying
DSP boot anymore.

Luis Cupido.
CT1DMK.

----- Original Message -----
From: "Doug Bade" <[email protected]>
To: <[email protected]>
Sent: Thursday, May 22, 2003 2:21 AM
Subject: Re: [DSP-10] KDSP10 Info

>          Thank you Luis !!!!!!
>
>
>          Well I inserted a 74hct14 flying lead style into the clock line
> and used 2 gate's to double invert and it cleaned the clock up pretty as
> can be and the pll LOCKED !!!!!!!!!!!!!!!!!!!!!!!
>
>          I am testing and checkout as it has been a while but looks like
rx
> noise floor dropped 6 db or so maybe more .... -147 dbm is a 10db+ spike
in
> the spectral display...in ssb mode  with the rf amp all up and 1200 hz
> window... It works so far, but have not tried tx....
>
>          The clock may indeed be affected by feedthru but looks like that
> should no longer be an issue..... Thanks for the concurrence and idea... I
> will neaten it up and dead bug the ic or something neater...
>
> Doug KB8GVQ
>
>
>
>
> At 12:25 AM 5/22/2003 +0100, you wrote:
> >Hi Doug,
> >
> >I went thought the trouble of using an inverter (unused one on some HC04
> >chip)
> >and change the software of the DSP to invert the logic of that signal to
get
> >it
> >sharp edge.
> >However most of the folks said to me that it was not necessary.
> >I blame the feedthrough capacitor I have at the DSP box (too big 4n7)
> >maybe that explain why others did not had this problem.
> >Don't know if this matches your case, of if it is of any help.
> >
> >Good luck.
> >Luis Cupido.
> >CT1DMK.
> >
> >
> >----- Original Message -----
> >From: "Doug Bade" <[email protected]>
> >To: <[email protected]>
> >Sent: Wednesday, May 21, 2003 11:57 PM
> >Subject: RE: [DSP-10] KDSP10 Info
> >
> >
> > >          More info... udiag1 will not run, udiag2 will not run..
> > >          Data clock and ena leads are toggling on main 12x.00 pll.
output
> > > of DO pin is high rail constantly, vco sitting at 129.0 mhz with 5v
railed
> > > on control line
> > >
> > >          PLL LMX1501a is not accepting the programming it is sent..
> > >          Clock is sloppy with long arcing sweep up on leading edge ...
is
> > > this normal????
> > >          I tried adding pull-up to clock, and it did clean up
transition,
> > > but no lock either...
> > >
> > >          DO output never ever changes.... u107 is getting serial
enable
> > > pulses, data is going to pll chip, enable toggles on pll... but not
> > > accepting load...
> > >
> > > Doug
> > >
> >
> >
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