[DSP-10] KDSP10 Info

[Luis Cupido]

Hi Doug,

I went thought the trouble of using an inverter (unused one on some HC04
chip)
and change the software of the DSP to invert the logic of that signal to get
it
sharp edge.
However most of the folks said to me that it was not necessary.
I blame the feedthrough capacitor I have at the DSP box (too big 4n7)
maybe that explain why others did not had this problem.
Don't know if this matches your case, of if it is of any help.

Good luck.
Luis Cupido.
CT1DMK.


----- Original Message -----
From: "Doug Bade" <dbade@clecom.com>
To: <dsp-10@mailman.qth.net>
Sent: Wednesday, May 21, 2003 11:57 PM
Subject: RE: [DSP-10] KDSP10 Info


>          More info... udiag1 will not run, udiag2 will not run..
>          Data clock and ena leads are toggling on main 12x.00 pll. output
> of DO pin is high rail constantly, vco sitting at 129.0 mhz with 5v railed
> on control line
>
>          PLL LMX1501a is not accepting the programming it is sent..
>          Clock is sloppy with long arcing sweep up on leading edge ... is
> this normal????
>          I tried adding pull-up to clock, and it did clean up transition,
> but no lock either...
>
>          DO output never ever changes.... u107 is getting serial enable
> pulses, data is going to pll chip, enable toggles on pll... but not
> accepting load...
>
> Doug
>