[DSP-10] Having PLL Problems

Mon, 4 Aug 2003 18:54:39 -0700

Christopher:

Here are a few suggestions to help get you going.  I always find that it is
most-useful to test individual stages of a design, rather than everything at
once.

First, the +10T and +10R circuits:  There was an issue that Bob outlined on
his web page (http://www.proaxis.com/~boblark/dsp10.htm) that discusses the
possibility of both +10T and +10R going high simultaneously.  A lockout
diode called "SR105" will keep this from happening.  Go to his web page,
search for "SR105" and add that diode.  Do this no matter what.....you do
NOT want both the transmit and receive stages to be enabled at the same
time.

Okay, step back a minute, you say neither are high right now.  Check the +10
on the opposite side of the FET devices (Q105 and Q106).  Check pins 1 and 2
from U108 and see what they are at, and deduce from that whether the
transistors Q103 and Q104 should be switching or not.  Quite simply, a high
value on the collector will cause the FETs to close, much like a switch (my
apologies if you know this, I'm uncertain where you're at with things).  In
the end, you should be able to see that a low voltage for QA or QB (outputs
of U108) should cause Q105 and Q106 to conduct.  Again, be careful to not
have both high simultaneously.

You should be able to completely debug this stage prior to having to fuss
with the 2181 board feeding the serial latch U108, etc.

One additional thought is to bridge a small wire from the base of say Q103
to ground.  This should cause +10T to assert.  Grounding the base of Q104
should cause +10R to assert.

I found it confusing which direction to mount the FETs into the board.  The
only difference is the Zener diode.  Disconnect all load wires for both +10T
and +10R and make sure you don't have a short to ground on any of the load
points (and make sure +10T and +10R NEVER turn on simultaneously before
turning on any of the RF stages.  Again, add SR105 with any diode like a
1n4152).

Okay, now the oscillators.  You have verified the 10 MHz oscillator makes it
to the input of the PLL chip.  This is good.  From here, I'd suggest you
verify the oscillator itself (the 19.68 or 122 MHz) without the PLL in the
loop.  Again, this is a divide-and-conquer approach that will be useful.

For this, I have some procedures posted on the internet:

  http://users.easystreet.com/rhayward/dsp10/index.html

>From there, click on the "pll tuneup procedures."

What I suggest is that you break the loop between the PLL and the
voltage-controlled oscillator.  You will need a variable resistor of some
sort, like a 10K or whatever.  Feed what the output of the PLL (D0, pin 5
from U104, for example) with a variable voltage between 0 and 5 volts.
Remember, you are feeding the oscillator, not the PLL.  The idea is that as
you vary this voltage bias on to the four varactors (FMMV2101 diodes), the
inductance in the resonant circuit will change slightly.

Your frequency counter should be able to see this circuit just fine (IMHO).

Okay, so here's what might happen.  Place the variable resistor on to the
voltage-controlled oscillator and vary the frequency (by varying the voltage
on the variable resistor).  You might get an oscillation at either the top
voltage, or the bottom voltage, but perhaps not both.  The inductange in
L102 gives you some range to adjust this.  In addition, the capacitance at
C117 and C118 (if I remember) will help provide the resonant circuit.  I'm
//guessing// the problem is that the tuning range isn't providing the right
frequency for the PLL (I had this problem).

Adjust the inductance of L102 as per the discussion.  You may need to lower
C117 a little bit.

(Do the same thing for both VCO's:  19.68 MHz and the 122 MHz VCO).

Don't mess with the PLL circuit AT ALL until you can see a nice wide range
of frequencies between 124 to 128 MHz on this stage.  After this works for
you, THEN (and only then) you can re-connect the PLL to the circuit.  Use
the UDIAG3 program on the web page to sweep the frequency.  This program
will set the frequency across the entire 4 MHz range in 100 KHz steps,
providing enough time for you to see each step on a frequency counter.

Other suggestions include looking at Bob's UDIAG2 and UDIAG1 programs.

I cannot stress enough the importance of breaking the PLL loop by removing
the loop (like lifting resistor R105).  Yes, you may need a spare resistor
or two.  If you want any parts (spare resistors mainly, perhaps I have a
spare cap or two), email me with your address and I can USPS them to you
(TAPR has discussed providing a couple of spares for this exact reason).
Once you have each individual VCO running freely, THEN you can re-connect
the PLL, and let the 2181 board download the latches, etc.

Let me know if this helps.  Good luck, and please let the group know how
things progress for you.  The DSP-10 is a blast to operate once you have
things running.

73,
  Roger Hayward
  ARS KA7EXM

-----Original Message-----
From: [email protected] [mailto:[email protected]]On
Behalf Of Christopher Michael Best
Sent: Monday, August 04, 2003 1:04 PM
To: [email protected]
Subject: [DSP-10] Having PLL Problems

        Thanks for the recent discussion, and solutions on the serial
clock pulse being rounded.  I used two inverters on a 74HC04 to square up
the signal, and now it appears that my serial problems are solved.
(Another step closer to getting on the air!)

        I am still having some problems with both PLL in my system. Both
of the PLL's are outputting 0hz (No output) on my frequency counter.  Both
of the synthesizers are recieving a clean 10MHz signal from the Epson
crystal
oscillator.  Voltages on both synthesizer appear to be alright, 4.72V on
the drain of Q101, and 3.67 on the drain of Q4. U107, and U108 voltages
are as stated on Bob's PLL diagnostics sheet. Pin six of the U6 op-amp is
on the bottom rail at .49V.

        Is it possible that both of my J310 FETS are dead? They were mailed
to
me in a regular envelope, so they might have been damaged in transit.

                        Thanks,
                         Christopher M. Best

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