[DSP-10] : Analog Devices ADSP 2181Substitution

[John Stephensen]

I see that between the time my old ViewSonic monitor expired and I received
the new one, there has been some discussion of my QEX article. Since the
next installment won't be published for a few months I'll provide some more
information here. This design won't execute ADSP-2181 code but it does
provide more processing power than the 2181 and would be inexpensive to
replicate. At least for me, it is more suited to experimentation than the
$300-1000 DSP evaluation boards.

I initially spent some time compiling information on what DSP hardware was
available that could be used in home construction of a DSP radio. The
initial design was constrained to use parts with lead spacings greater than
37 mils so that a human being can assemble it. This precludes using
high-density gate arrays and 1000 MIPS DSPs since they all come in ball grid
array (BGA) packages and are very expensive to use in small manufacturing
runs. However, the amount of processing required for the narrow-band modes
that amateurs use is fairly small and there are inexpensive parts available.
I partitioned the digital portion of the design onto multiple boards to
allow experimentation. Since the cost of PCB manufacturing doesn't increase
much with size, I lay out a number of boards and combine them into one
Gerber file for manufacturing. Each board accomodates a chip or chip set
that I'll be experimenting with. Interface logic is in CPLDs that I program
as the project progresses. I'm using Atmel MAX3000A series CPLDs in PLCC
packages as they can be socketed and interface to 2.5, 3.3 and 5 volt logic.

My initial project is replacing most of the analog portion of my homebrew
SSB transceiver with DSP.  There are 4 boards. The first centers around an
Atmel AT94K10 FPSLIC which is a 576-cell FPGA plus 20KB of RAM, a 20 MIPS
8-bit AVR RISC processor and 2 serial ports in an 84-pin PLCC package. The
board contains RS-232 and RS-485 drivers and receivers for the serial ports
and a socket for a Cypress SL811 USB host and device controller chip. The
FPGA connects to 4 RJ-45 jacks via 3.3-volt RS-422 style differential
drivers and receivers. These carry a clock, a channel of 0-10 MBPS serial
data to DACs and 2 channels from ADCs located on other boards. There is also
a socket for PLCC UVPROMs or EEPROMs up to 512K x 8 for look up table and
code storage.

The second board contains an Alesis DSP, dual 24-bit ADC and dual 24-bit
DAC. The DSP is in a 16-pin SOIC package and executes up to 50 MMAC/sec.
with 24 bit data. The AL3102 program is downloaded from the first board via
the RS-422 interface that later carries the digitized audio or IF signals.
I'm using one board for IF and one for audio but one board could do both
tasks if quadrature IF channels aren't needed. I put 4 RS-422 ports on the
main board to accomodate multiple boards for diversity reception
experiments.

The third board is mostly analog with either a 10.7 or 21.4 MHz 8 kHz wide
crystal filter, LNA, phase-locked oscillator with quadrature outputs and
four passive FET mixers to convert to and from the 16 kHz transmit and
receive IFs. There are two low-noise PGAs for the 16 kHz IF.

The fourth board consists of two 200 KSPS 24-bit DACs, two mixers, two
470-500 kHz filters and two buffer amplifiers. This is used as a high
dynamic range DDS to control the transmit and receive VFOs described in the
ATR-2000 article.

The code that I'm debugging uses the AL3102 to convert the two quadrature 16
kHz IF channels sampled at 48 KSPS to two 0-3kHz quadrature baseband
channels, provide image rejection and provide filtering before decimation to
8 KSPS. The AT94K10 operates on the 8 KSPS baseband signal using the FPGA
for additional filtering and the CPU for housekeeping tasks like AGC and
AVC. The transmit code will do the reverse. I'm not using the USB interface
yet, but it could carry the digitized baseband signal to a PC for additional
processing or interface to USB speakers and microphones.

73,

John
KD6OZH