[ARC5] JFET in ARC-5 TX oscillator socket

[Dennis Monticelli]

I forgot that it was a Hartley configuration.  You're right.  Output would
probably be low at the source node.

One way around that would be to choose a high Vp (pinchoff) JFET with a high
Idss rating and still protect it with a cascode device or else bias the
drain from a separate voltage source.   I think the appropriate choice would
be a J111 (2N4856 or PN4856 is the same) or J108 (PN5432 is the same)  The
latter is the most beefy.  In all cases the BV is at least 25V.  But these
JFETs have more transconductance than the 1626 so the gate-source swing will
be less than the grid-cathode swing for a given current draw.  The optimum
would be to change the tap on the coil but this is something most of us
would prefer not to do.

Dennis AE6C

On Sat, Jul 4, 2009 at 10:31 AM, Ian Wilson <ianmwilson73 at gmail.com> wrote:

> Not sure that beefing up the voltage dropped across a composite device
> would
> help, since it's a Hartley oscillator. The voltage swing is determined by
> the
> current through the device and the magnitude of the grid bias voltage
> developed
> (I think). Some other SS compound might have the right characteristics,
> though?
>
> 73, ian K3IMW
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